Chemical-mechanical polishing (CMP) is a modern technique for planarizing a layer of material. In certain circumstances, CMP is used to planarize a layer of isolation material that is grown or deposited between active areas of a semiconductor substrate. The term “active area” is commonly used to describe that portion of the semiconductor substrate on which components are built, such as transistors, capacitors and resistors. As is well known in the art, in order to prevent conduction or crosstalk between active areas on a substrate, an electrical isolation material (e.g., silicon dioxide), referred to herein as an isolation material, is placed between the active regions. This may be accomplished by etching trenches into the substrate between the active areas, and thereafter filling the trenches with the isolation material. What typically results are isolation structures between the active areas.
FIG. 1 illustrates a semiconductor device 100 at a stage after which a layer of isolation material 150 has been deposited over a substrate 110. The substrate 110 of FIG. 1 includes active areas of silicon 120 (e.g., areas A, B, C, D) separated by trenches 130. In the device 100, the trenches 130 between active areas A, B and C are much narrower than the trench 130 between active areas C and D.
As is illustrated in FIG. 1, the layer of isolation material 150 often does not have a flat topography, but has significant protrusions above the active areas A, B, C. However, where there are no active areas, such as between active areas C and D, or alternatively when an active area is isolated from the other densely populated features, such as over active area D, the layer of isolation material 150 is relatively flat. As is well known in the art, it is desirable that the layer of isolation material ultimately be flat, even if the aforementioned active areas cause it to have topography. Accordingly, layers of isolation material having topography are typically subjected to a CMP operation.
FIG. 2 illustrates the device 100 of FIG. 1 after subjecting it to a CMP operation. The CMP operation stops when it reaches the stop layer 220, thus leaving the layer of isolation material 210 slightly below the top of the stop layer 220. This can be seen in the areas between active areas A and B and active areas B and C. Unfortunately, where there is a significant distance between active areas, such as between active areas C and D, the layer of isolation material 210 may be overpolished. When the overpolishing occurs, significant dishing 230 may result, and thus a non-planarized surface may result. Moreover, the overpolishing may completely remove the stop layer 220 in those circumstances that it exists, thus affecting the top surface of the active area D. In extreme circumstances, a significant portion of the top surface of the active area D may be polished away. The overpolishing will impair device performance, reliability and yield. It is believed that the overpolishing for active area D is caused by the unevenness in pressure that is applied because of the difference in the area density between the area encompassing active areas A, B, and C and the area which only has active area D, as well as the process selectivity, e.g. physical or chemical selectivity, that may be a result of differences in pre-polish topography.
Accordingly, what is needed in the art is a method for manufacturing a semiconductor device that addresses the aforementioned CMP issues.